New Source Heterojunction Structures with Relaxed/Strained Semiconductors for Quasi-Ballistic Complementary Metal–Oxide–Semiconductor Transistors: Relaxation Technique of Strained Substrates and Design of Sub-10 nm Devices

Abstract

We have studied new abrupt-source-relaxed/strained semiconductor-heterojunction structures for quasi-ballistic complementary metal–oxide–semiconductor (CMOS) devices, by locally controlling the strain of a single strained semiconductor. Appling O+ ion implantation recoil energy to the strained semiconductor/buried oxide interface, Raman analysis of the strained layers indicates that we have successfully relaxed both strained-Si-on-insulator (SSOI) substrates for n-MOS and SiGe-on-insulator (SGOI) substrates for p-MOS without polycrystallizing the semiconductor layers, by optimizing O+ ion implantation conditions. As a result, it is considered that the source conduction and valence band offsets ΔEC and ΔEV can be realized by the energy difference in the source Si/channel-strained Si and the source-relaxed SiGe/channel-strained SiGe layers, respectively. The device simulator, considering the tunneling effects at the source heterojunction, shows that the transconductance of sub-10 nm source heterojunction MOS transistors (SHOT) continues to increase with increasing ΔEC. Therefore, SHOT structures with the novel source heterojunction are very promising for future quasi-ballistic CMOS devices.