New quantization error assessment methodology for fixed-point pipeline FFT processor design

Abstract

Since the blooming of mobile computing era, all semiconductor providers are seeking to provide low-power, high-performance, high-compact solutions to consumers. System on Chip (SoC) is a prominent solution for integrating multiple functions into one compact size chip. However, for many new applications with high intensive computing demands, such as GPS location, High Definition (HD) video recording and processing, Orthogonal Frequency-Division Multiplexing (OFDM), etc. System designers usually utilize fixed point algorithms other than floating-point algorithms as a trade-off between precession and memory occupation. One of the challenging works in designing a fixed-point FFT processor is to assess the quantization error introduced by wordlength configuration. An optimized wordlength configuration will eliminate the output quantization error in some extent, and save a large amount of memory space, which has become a crucial part of SoC/ASIC design. In this paper, we proposed a quantization error model based method to assess the output SQNR (Signal-to-Quantization-Noise Ratio), and we thoroughly discussed a matrix representation of a radix-22 Decimation-In-Frequency (DIF) FFT quantization error propagation model. In addition, we comprehensively analyze and disclose the quantitative relationships among wordlength configuration, fixed-point FFT architecture and output SQNR. A new wordlength configuration method named PMBM (Performance-Memory Balanced Method) for fixed-point pipeline FFT processor is also proposed. Eventually, we testified our method in both a 256-point FFT and a 1024-point FFT using SystemC platform. The experiment results show that our method significantly decrease the memory usage of a pipeline FFT by 26% (256-point) and 30% (1024-point) respectively. We implemented a 16K-point FFT ASIC to verify our method.