Abstract
A clock recovery IC for optical fibre communication at multigigabit/s is proposed. The clock frequency extracted corresponds to half the bit rate. The 2:1 frequency division is carried out by a double balanced mixer and the frequency selection by an SAW filter. Circuit simulations are based on a standard 2 μm silicon bipolar technology. The circuit was optimisd at 3.4 Gbit/s for a power consumption of 220 mW with a 1.7 GHz SAW filter (Q = 340). The dynamic clock phase jitter, estimated from circuit simulations, is less than 0.5°. Circuit simulations predict that the operating bit rate may be exended up to 4.5 Gbit/s.
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