Abstract
A first theoretical analysis is given based on a new model of GaAs MESFET's which considers the inherent effects of a free-surface depletion layer between source and gate as well as between gate and drain. Change of surface potential according to the input gate voltage causes variable series resistance and variable gate capacitance to be added to the intrinsic FET. The parasitic effects are now quantitatively estimated and an improved guideline for the design and the fabrication process is given. Detailed calculation of the effects of device parameters for recessed gate structure and some comments on the optimization of n+-layers in self-aligned structure are included. The effects of the interfacial depletion layer between active layer and substrate is also estimated in terms of drain voltage and the ratio of total deep levels density in the substrate to donor density in the active layer.
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