New Methodology for Parasitic Resistance Extraction and Capacitance Correction in RF AlGaN/GaN High Electron Mobility Transistors

Abstract

This paper presents a novel approach to the efficient extraction of parasitic resistances in high electron mobility transistors (HEMTs). The study reveals that the gate resistance value can be accurately determined under specific forward gate bias conditions (Vg = 1.0 V), although the gate resistance value becomes unreliable beyond this threshold (Vg > 1.0 V) due to potential damage to the Schottky contact. Furthermore, by examining the characteristics of the device under a cold-FET bias condition (Vds = 0 V), a linear correlation between the gate and drain current is identified, enabling an estimation of the interdependence between the drain and source resistance using the proposed method. The estimation of parasitic pad capacitance (Cpg and Cpd) from Dambrine’s model is refined by incorporating the depletion layer capacitance on the gate side during the pinch-off condition. To validate the accuracy of the extracted parasitic capacitance and resistance values obtained from the new method, small-signal modeling is performed on a diverse range of measured devices.