New linear systolic arrays for the string comparison algorithm

Abstract

VLSI technology has achieved tremendous success in revolutionizing computer design with processor arrays. Foster and Kung, in [1] propose a linear systolic array for the string comparison algorithm. This solution is based on a regular movement of the pattern and the input string in opposite directions keeping the results (1 bit values) resident in the array. A special technique, requiring two wires is applied to unload the result array in a pipeline with the input string so no extra time is required. Disadvantages of this approach are 50% maximum processor efficiency and intensive memory access when string sizes are greater then the array size. We use several algorithm transformation techniques to transform the algorithm into a system of Affine Recurrence Equations (ARE), [2] and then apply the data broadcast elimination method [3]. A system of Uniform Recurrence Equations (URE) is resulted and then mapped [4] on VLSI processor arrays. The folding transformation [5], is then applied to establish the optimal implementations by selecting the plane achieving maximum symmerty and the vector of interlocking property with minimal norm. The implementations obtained result in more efficient VLSI processor arrays.