New layout strategies with improved matching performance

Abstract

In this paper, the systematic mismatch error in integrated circuits due to gradient effects is modeled and analyzed. Three layout strategies with improved matching performance are reviewed and summarized. The hexagonal tessellation pattern can cancel quadratic gradient errors with only 3 units for each device and has high area-efficiency when extended. Both the Nth-order circular symmetry patterns and Nth-order central symmetry patterns can cancel up to Nth-order gradient effects between two devices using 2N unit cells for each one. Among these three techniques, the central symmetry patterns have the best-reported matching performance for Manhattan structures; the circular-symmetry patterns have the best theoretical matching performance; and the hexagonal tessellation pattern has high density and high structural stability. The Nth-order central symmetry technique is compatible to all IC fabrication processes requiring no special design rules. Simulation results of these proposed techniques show better matching characteristics than other existing layout techniques under nonlinear gradient effects. Specifically, two pairs of P-poly resistors using 2nd and 3rd-order central symmetry patterns were fabricated and tested. Less than 0.04% mismatch and less than 0.002% mismatch were achieved for the 2nd and the 3rd-order structures, respectively.