New Insights on Dynamic Voltage Scaling of Multiphase Synchronous Buck Converter: A Comprehensive Design Consideration

Abstract

This paper comprehensively investigates the power-related issues and introduces new control schemes in dynamic voltage scaling (DVS), which is now used in modern multi-core processor and multiprocessor system-on-chip to reduce operational voltage under light load conditions. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experimental results. CdV/dt compensation for removing the adaptive voltage positioning effect and a novel nonlinear control scheme for smooth transition are proposed for dealing with fast-voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification delta to further reduce the dynamic loss. For experimental verification, a 200 W, six-phase synchronous buck converter is implemented with the proposed schemes.