New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties

Abstract

Figures-of-Merit (FOMs) are widely-used to compare power semiconductor materials and devices and to motivate research and development of new technology nodes. These material- and device-specific FOMs, however, fail to directly translate into quantifiable performance in a specific power electronics application. Here, we combine device performance with specific bridge-leg topologies to propose the extended FOM, or X-FOM, a Figure-of-Merit that quantifies bridge-leg performance in multi-level (ML) topologies and supports the quantitative comparison and optimization of topologies and power devices. To arrive at the proposed X-FOM, we revisit the fundamental scaling laws of the on-state resistance and output capacitance of power semiconductors to first propose a revised device-level semiconductor Figure-of-Merit (D-FOM). The D-FOM is then generalized to a multi-level topology with an arbitrary number of levels, output power, and input voltage, resulting in the X-FOM that quantitatively compares hard-switched semiconductor stage losses and filter stage requirements across different bridge-leg structures and numbers of levels, identifies the maximum achievable efficiency of the semiconductor stage, and determines the loss-optimal combination of semiconductor die area and switching frequency. To validate the new X-FOM and showcase its utility, we perform a case study on candidate bridge-leg structures for a three-phase 10 kW photovoltaic (PV) inverter, with the X-FOM showing that (a) the minimum hard-switching losses are an accurate approximation to predict the theoretically maximum achievable efficiency and relative performance between bridge-legs and (b) the 3-level bridge-leg outperforms the 2-level configuration, despite utilizing a SiC MOSFET with a lower D-FOM than in the 2-level case.