Abstract
A new 1-D linear-phase interpolation algorithm is proposed in this paper. For every M output points the new algorithm reduces the number of multiplication operations from the best known N/2 to N/4+N/(2M), while it requires 3N/4+3N/(2M)+2M-2 addition operations, which may be smaller or greater than the best known N-M, where N and M are the interpolator tap number and interpolation factor respectively. The algorithms are further extended to 1-D nonlinear-phase interpolation and 2-D linear-phase interpolations. Systolic array realization for 1-D linear-phase algorithm is also given, which is highly regular and suitable for VLSI implementation. The algorithm assumes a filter order of an even multiple of the interpolation factor. The condition is not too restrictive, because the interpolator tap number can be shown to be empirically proportional to the interpolation factor. Moreover, the drawback of possibly increased filter order could be overcompensated by the saving of close to N/2 multiplication operations, as well as the gain in tighter filter specifications.
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