New designs for a sign detector and a residue to binary convertor

Abstract

In the paper, two algorithms have been developed. The first one has been exploited in implementing a residue to binary convertor (R/B) for the moduli set {2k − 1, 2k, 2k + 1}. The new convertor is memoryless, which implies that its upper bound is not limited by a memory size. Furthermore, this convertor represents a new significant reduction in both the hardware requirements and conversion time. A full conversion cycle consists of three consecutive additions each of (k + 1) bits. The same implementation can be modified slightly to implement a sign detector for the same moduli set. Another algorithm has been developed based on the mixed radix conversion technique. This algorithm was used to implement a new sign detector. This new detector is very efficient in the sense that it requires only two addition cycles each of (k + 1) bits. A further reduction in execution time is possible if pipelining is used. All the circuits presented can be implemented using VLSI technology, which gives rise to a reduction in the integrated circuit area.