Abstract
The authors discuss the impact of device cell geometry on the safe operating area (SOA) of IGBTs (insulated-gate bipolar transistors). Two-dimensional computer simulations of the electric field distribution and avalanche breakdown have been performed for a variety of cell geometries. Simulation of the square-cell and linear-cell geometries used in previous devices showed that the SOA is determined by a spherical junction formed at the corners of the cells. To circumvent this problem, two cell topologies are proposed: the rounded-end-linear (REL) cell and the atomic-lattice-layout (ALL) cell. With the REL cell, the breakdown voltage is improved to that of a cylindrical junction. With the ALL cell, the breakdown voltage is even further improved to that of a saddle junction. The modeling predicts an improvement in the SOA current density by a factor of 1.9 and 2.6, respectively, and these have been experimentally confirmed. The ALL cell design also reduces the input gate capacitance by half and increases the contact area to the emitter by a factor of 5 over the linear cell geometry. >
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