New built-in self-test technique based on addition/subtraction of selected node voltages

Abstract

For a faulty circuit, the sensitivity of different node voltages with respect to different faults is not the same. To make use of the node voltages to detect and/or isolate faults, access to the internal circuit nodes is required. Techniques like voltage scan can be adopted to achieve this put-pose but considerable hardware overhead are incurred. Practically, not all of the circuit nodes are necessary to achieve the maximum fault coverage. In this paper we propose a new built-in self-test (BIST) technique, making use of the addition/subtraction of a small pre-selected set of circuit node voltages to achieve high fault detection and location while hardware overhead is small when compared with the voltage scan approaches.