New Approach to Negative Differential Conductance with High Peak-to-Valley Ratio in Silicon

Abstract

In this paper we report a new approach to realize negative differential conductance (NDC) with a high peak-to-valley (P/V) ratio in silicon metal-oxide-semiconductor field effect transistors (Si MOSFETs). A P/V ratio of as large as 10 at room temperature has been demonstrated by controlling the effective biasing to p-MOSFETs fabricated on a silicon-on-insulator (SOI) wafer. Although the band-to-band tunneling current is utilized, the excess tunneling current which has ever limited the P/V ratio in the Si Esaki diode is eliminated in the proposed method. Higher P/V ratio will enable us to incorporate NDC functionality into future Si large-scale integrated (LSI) circuits and open up new possibilities for LSI applications.