New approach for the ordering of gate permutation in one-dimensional logic arrays

Abstract

The one-dimensional gate permutation problem is transferred into a new one of achieving an optimum gate permutation under the constraint of a predetermined adjustable maximum number of tracks. A fast and efficient constructive algorithm is proposed to solve it. The algorithm has the advantage of uniformly distributing the local congestion so that optimum permutation with the required track number can be obtained. The experimental results show that it is a fast algorithm and gives better solutions than other constructive algorithms. Moreover, it can be used as an improvement algorithm by using a modified ratio-cut technique. The improvement algorithm iteratively improves the previous solutions, and thus results comparable to the simulated annealing approach can be obtained in less CPU time.