New approach for continuous time sigma delta modulators

Abstract

A new continuous-time sigma-delta (SD) modulator that is suitable for implementation in low-voltage nanoscale CMOS technology is proposed in this paper. The proposed modulator, called PW-SD modulator, can be obtained by replacing the quantizer and sampler of the well-known continuous-time multibit SD modulator for a comparator with hysteresis and a new sampler clocked at higher rate. The output of the PW-SD modulator is a modulated pulse-width (PW) signal with resolution comparable to the resolution of the output of the multibit modulator as shown by simulation results. Despite these differences, both modulators have the same performances and low-frequency dynamic. The main advantage of the proposed modulator as compared to the multibit counterpart is the substitution of the multibit quantizer (a bank of comparators) for only one comparator and the multibit DAC in the feedback path for a single-bit one. Furthermore, it is expected that PW-SD modulator consumes less power and occupies less silicon area. It is targeted to find bandwidth and resolution specifications of 12 MHz and 12 bits, respectively, in a 90 nm digital CMOS technology.