Neural network model for testing stuck-at and delay faults in digital circuit

Abstract

The automatic test pattern generation techniques using artificial neural networks are studied. First, an optimal neural network model of digital circuits is investigated. The network model can represent a logic circuit by the minimal number of neurons. It is shown that there exist optimal neural networks for arbitrary logic circuits. We can get the network parameters by solving a system of linear equations. Second, a new energy model for delay faults testing of digital circuits is presented, which is based on the optimal neural network models. Third, it is shown that the test generation approach using the optimal neural network model can reduce the search space, and has better computation efficiency if compared with the circuit test methods using Hopfield binary neural network.