Neural dynamics in reconfigurable silicon

Abstract

A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also using the same to interface with actual cells in applications like a dynamic clamp. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components also consists of floating-gate transistors. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights.