Network-on-Chip Validation and Debug

Abstract

Network-on-Chip (NoC) has become the standard interconnect solution to address the communication requirements of many-core Chip Multiprocessors (CMPs). It is well known that the network performance and power consumption depend critically on the traffic behavior in the interconnection network. The more critical the NoC becomes, the more reliable it needs to be. NoC architectures available in commercial System-on-Chip (SoC) such as Intel Xeon E5 have shown 25.6% NoC errors out of the total post-silicon errors. In addition to the common challenges of verifying any SoC component, NoC possesses a unique set of challenges arising from its inherently parallel communication nature, security concerns, dynamic behavior, and added measures for reliable data transfers. This makes the task of NoC verification ever more cumbersome. This chapter outlines the unique NoC verification challenges and describes the ways to counter them. Solutions such as increasing observability through trace buffers, boundary scan, as well as both functional and non-functional validation techniques are presented. It also describes pitfalls of traditional methods and how recent research improved them. This chapter provides an overview of the existing NoC verification methodologies and outstanding research problems.