Network on metachip architectures

Abstract

The size of systems on a chip is limited by our ability to design and fabricate such systems, staying within the appropriate costs depending on the application. In this paper, we propose a divide-and-conquer approach, Quilt Packaging®, to be utilized for reducing the fabrication costs of large digital systems by partitioning them into a quilted that offers integration density and performance merits surpassing the traditional system-on-chip. The physical partitioning and the network-on-a-quilt are closely linked, and should be designed concurrently. For this purpose, we present calculations on the silicon cost of the interconnects and partitioning, discuss the network granularity, and propose a multiprocessor design around a quilted modular network, offering novel techniques to improve the performance and enable true heterogeneous integration. Specifically, the silicon costs of the quilting method are demonstrated to be around 1% of the chip area, while the yield benefits can be in the tens of percents regime. The metachip concept enables the combination of standard high-density memory technologies and wide-bus access with improved performance, typically at least doubling the amount of memory vs. single-chip CMOS. Our modular quilted network enables the integration of non-CMOS chips into the quilt.