Network accelerator for parallel discrete event simulations

Abstract

The simulation time of parallel and distributed discrete event simulation is the heart rate for as-fast-as execution schemes. Agreeing upon a global simulation time and distributing it to the simulation processes can be improved by exploiting or redesigning the network hardware. In this paper, we present such an approach that offloads simulation time calculations to network switches in order to speed up the steps where time advance requests are made and time advance grants are waited. By reducing the waiting time for time advancement, we aim to improve the overall performance of the parallel simulations. The measurements from the FPGA-based hardware setup and the results from our network simulations show that overall performance can be improved when time management calculations are offloaded to the network switches. Additionally, the transient message problem is also solved within the network by not allowing the time control messages to bypass the time-dependent events. The network acceleration of the region-based event distribution is also studied, and offloading the region matching tasks to the network switches is found to be feasible to reduce the costs of node-based calculations, especially for fast-moving regions. In this study, we consider High Level Architecture (HLA) for simulation infrastructure and fat tree topology for high-performance networking.