Nesting ring architecture of multichip optical network on chip for many-core processor systems

Abstract

Optical network on chip (ONoC) is an attractive solution for multicore/many-core processor systems due to its high power efficiency and enormous bandwidth. However, as increasing numbers of cores need to be interconnected, the scalability of a many-core processor on a single chip is limited by its process yield and power density. A multichip architecture is, therefore, proposed to improve the scalability of ONoC. In multichip architectures, the throughput and traffic delay rely on both the intrachip and interchip networks. To exploit the advantages of multichip systems, first we propose a multichip ONoC architecture for a many-core processor system that employs a nesting ring topology. The design principles of multichip systems of different sizes are then investigated to achieve higher throughput and lower delay. These principles include the number of chips and the number of cores per chip, which are considered jointly for the first time. Finally, we evaluate the performance of the proposed architecture, implemented in 240-core and 400-core systems, respectively, and compare it to two other traditional ONoC architectures with respect to throughput and end-to-end (ETE) delay. The results show that the proposed multichip system exhibits good scalability, achieves high throughput, and provides low ETE delay.