Negative capacitance in a ferroelectric-dielectric heterostructure for ultra low-power computing

Abstract

Introduction: It is now well recognized that energy dissipation in microchips may ultimately restrict device scaling – the downsizing of physical dimensions that has fuelled the fantastic growth of microchip industry so far. However, energy dissipation in electronic devices has even bigger consequences. Use of electronic equipments in our daily life is increasing exponentially. As a result, energy dissipation in electronic devices is expected to play an increasingly significant role in terms of national energy needs [1-6]. But there is a fundamental limit to how much the dissipation can be reduced in transistors that is in the heart of almost all electronic devices. Conventional transistors are thermally activated. A barrier is created that blocks the current and then the barrier height is modulated to control the current flow. This modulation of the barrier changes the number of electrons exponentially following the Boltzmann factor exp(qV/kT). This in turn means that to change the current by one order of magnitude at least a voltage of 2.3kT/q (that translates into 60 mV at room temperature) is necessary. In practice, a voltage many times this limit of 60 mV has to be applied to obtain a good ON current to OFF current ratio. Because this comes from the Boltzmann factor that is a fundamental nature of how electrons are distributed in energy, it is not possible to reduce the supply voltage in conventional transistors below a certain point, while still maintaining a healthy ON/OFF ratio that is necessary for robust operation. On the other hand, continuous down scaling is putting even larger number of devices in the same area thus increasing the energy dissipation density beyond controllable and sustainable limits. This has been termed as the Boltzmann’s Tyranny [2] and it has been predicted that unless new principles are found based on fundamentally new physics, the transistors will die a thermal death [4].