Negative bias temperature stress and annealing effects in p-channel power VDMOSFETs

Abstract

The effects of negative bias temperature stressing and subsequent low gate bias annealing on threshold voltage in p-channel power VDMOSFETs are analysed in terms of the mechanisms responsible for underlying changes in the densities of gate oxide-trapped charge and interface traps. Rather significant stress-induced degradation does not seem affected by subsequent annealing under the negative gate bias. Alternatively, either zero or positive gate bias annealing removes the portion of stress-induced oxide-trapped charge while creating the additional interface traps. The post-stress generation of interface traps under the positive oxide field is ascribed to processes arising from a reversed drift direction of positively charged species. The influence of external bias on annealing phenomena weakens in the case of extended stressing, suggesting that extended stress moves the trapped charge to energetically deeper oxide traps, which are more difficult to anneal. The temperature is found to play important role in the post-stress phenomena.