Negative bias temperature instability: What do we understand?

Abstract

We present a brief overview of negative bias temperature instability (NBTI) commonly observed for in p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) when stressed with negative gate voltages at elevated temperatures and discuss the results of such stress on device and circuit performance and review interface traps and oxide charges, their origin, present understanding, and changes due to NBTI. Next we discuss some of the models that have been proposed for both NBTI degradation and recovery and p- versus n-MOSFETs. We also address the time and energy dependence effects of NBTI and crystal orientation. Finally we mention some aspect of circuit degradation. The general conclusion is that although we understand much about NBTI, several aspects are poorly understood. This may be due to a lack of a basic understanding or due to varying experimental data that are likely the result of sample preparation and measurement conditions.