Near-threshold SRAM design with dynamic write-assist circuitry

Abstract

Increasing process variation and reducing supply voltage can significantly degrade the write-ability of near-threshold SRAM cells. Meanwhile, the dynamic write assisting techniques and the high write latency at near-threshold V dd makes the traditional static performance metrics no longer capable. In this paper, we adopt transient negative bit-line voltage technique (T-NBL) to improve cell write-ability without disturb the read ability and data retention ability. And we propose a new set of performance metrics to fully access the performance of SRAM cells considering the dynamic nature of the write operation. Meanwhile, the efficient robustness consideration has been included. Statistical simulations with a 40nm technology design verify the proposed performance metrics.