Abstract
In deeply scaled CMOS technologies, two major non-ideal factors threaten the survival of the CMOS, i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel process monitoring circuit for low power applications. The proposed circuit is immune to voltage and temperature variation and achieves lower power consumption compared to a previous process monitoring circuit. The proposed process monitoring circuit is implemented using 45nm technology, and the proposed design reduces power consumption by 67% and area by 35.2% compared to the process monitoring circuit previously used.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
