Near-optimal Y-routed delay trees in nanometric interconnect design

Abstract

Performance-driven routing tree construction has immense research scope in today's VLSI circuit design. In this study, the authors focuss on delay efficient routing tree construction. Our current work encompasses two aspects of research. On the one hand, the authors consider the construction of cost-effective global routing trees with the recently introduced Y-interconnects, and on the other hand, we utilise this framework for verifying the supremacy of the two-pole and Elmore delay estimate for its high fidelity. The authors also incorporated fidelity measure for two-pole delay estimate. In order to ensure accurate computation of fidelity, (i) the authors propose new statistically proven formulae for the fidelity metric, and (ii) compute the fidelity values based on delay estimates for optimal and near-optimal trees. Our experiments on several randomly generated problem instances and benchmarks confirm once again the supremacy of fidelity of two-pole and Elmore delay estimates over that of linear delay. The two-pole delay estimate is also observed to exhibit higher fidelity compared to Elmore delay in most of the cases.