Near-interface oxide traps in 4H–SiC MOS structures fabricated with and without annealing in NO**Project supported by the National Key Basic Research Program of China (Grant No. 2015CB759600), the Natural Science Basic Research Plan in Shaanxi Province, China (Grant No. 2017JM6003), and the National Natural Science Foundation of China (Grant Nos. 61774117 61404098 and 61274079).

Abstract

Near-interface oxide traps (NIOTs) in 4H–SiC metal–oxide–semiconductor (MOS) structures fabricated with and without annealing in NO are systematically investigated in this paper. The properties of NIOTs in SiC MOS structures prepared with and without annealing in NO are studied and compared in detail. Two main categories of the NIOTs, the “slow” and “fast” NIOTs, are revealed and extracted. The densities of the “fast” NIOTs are determined to be and for the N2 post oxidation annealing (POA) sample and NO POA sample, respectively. The densities of “slow” NIOTs are and for the NO POA sample and N2 POA sample, respectively. It is found that the NO POA process only can significantly reduce “slow” NIOTs. However, it has a little effect on “fast” NIOTs. The negative and positive constant voltage stresses (CVS) reveal that electrons captured by those “slow” NIOTs and bulk oxide traps (BOTs) are hardly emitted by the constant voltage stress.