Near interface oxide trap capture kinetics in metal-oxide-semiconductor transistors: Modeling and measurements

Abstract

The traps situated in the oxide in the vicinity of the Si–SiO2 interface in metal-oxide-semiconductor (MOS) transistors, are studied. This is achieved using a new technique, based on the measurement of drain current transients and called T-CDLTS (tunnel-current deep level transient spectroscopy). For this, the traps are repeatedly filled with majority carriers using gate pulses which bias the device in accumulation. Each time the device returns in inversion, the drain current transient induced by the filling of the traps with minority carriers is monitored. A model for extracting the interface trap depth concentration profiles from the current transients is derived. It is based on Shockley–Read–Hall’s statistics [R. N. Hall, Phys. Rev. 87, 387 (1952), W. Shockley and W. T. Read, Phys. Rev. 87, 835 (1952)] and on the Heiman and Warfield tunneling model [F. P. Heiman and G. Warfield, IEEE Trans. Electron Devices ED-12, 167 (1965)]. The slow trap densities measured in a virgin device agree with those obtained in state-of-the-art MOS transistors using noise measurements. In virgin and stressed devices they also compare favorably with the trap densities obtained using a recently proposed charge pumping technique. The evolution, with the experimental conditions, of the trap concentrations measured is discussed with respect to that expected from the model. In some experimental conditions, a very good agreement is obtained while in some others, discrepancies are observed. These discrepancies are discussed as regard to the hypothesis introduced in the model.