NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization

Abstract

Semiconductor technologies bring the possibility of embedding billions of components in a chip, allowing the design of complex integrated circuits. However, such levels of integration are not free and delay uncertainties grow steadily, which is increasingly challenging. Quasi-delay-insensitive (QDI) design promises to cope with such challenges, being less timing constrained than synchronous or bundled-data designs. However, two barriers to its wider adoption are: 1) missing methods to automatically implement QDI circuits and 2) enabling QDI semi-custom design. This paper proposes a new QDI design method that extends the null convention logic (NCL) asynchronous template. Also, it describes an associated semi-custom design flow for the extended template, which uses conventional electronic design automation tools to synthesize QDI circuits down to layout. The method enables using the full power of synthesis and optimization commercial tools. Illustrating this, the ISCAS85 benchmarks take 35%–43% less gates to implement, compared with conventional, pattern-based NCL design. A comparison with the Uncle tool provides indication that the proposed method is indeed a flexible and powerful approach to design asynchronous QDI circuits. Lastly, 16-b multiplier designed with the method until the layout level exhibits 170%–240% larger operations/Watt compared with an equivalent NCL design, and an almost 400% better operations/mm2 figure.