NBTI Monitoring and Design for Reliability in Nanoscale Circuits

Abstract

Negative Bias Temperature Instability (NBTI) has become one of the major threats to circuit reliability in nanoscale-era. This paper presents a novel technique to monitor and tolerate NBTI in nanoscale circuits. First, it models NBTI impact on the gate output transition time, the simulation results show that NBTI can cause up to 8.56% increment to the transition time. Second, it presents a scheme to monitor the NBTI impact, the scheme is based on measuring transition time of the gate output. The proposed scheme converts the transition time increment into a voltage with a sensitivity of 0.50mV = ps, the simulation results show that the transition time increment can cause up to 80mV increment in the monitoring circuit output voltage. Third, it proposes a design for reliability technique to mitigate NBTI impact by applying a positive body bias to the PMOS transistors, simulations carried out on a 33-stage ring oscillator reveal that the technique reduces NBTI impact by 34% in 10 years operational life. To show its effectiveness, leakage overhead of the proposed technique is also analyzed.