Abstract
This article deals with a novel architecture for IP routing table construction, on the basis of a single set-associative hash table to support fast longest prefix matching (LPM). The proposed architecture uses two key techniques to lower table storage required drastically: (1) storing transformed prefix representations and (2) accommodating multiple prefixes per table entry via prefix aggregation. Given a set of chosen prefix lengths (called treads), all prefixes are rounded down to nearest treads before hashed to the table using their transformed representations so that prefix aggregation opportunities abound in hash entries. Significant table storage reduction makes it possible to fit a large routing table in on-chip SRAM, solving both the memory and bandwidth- intensive problems faced by IP routing. Simulation results on real routing tables show that the proposed architecture saves at least two folds of storage when compared with most known hash table- based design or trie-based design. In addition, our design enjoys fast lookups and incremental updates, with the worst-case lookup time upper-bounded theoretically by the number of treads (zeta) but found experimentally to be 4 memory accesses when zeta equals 8.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.