Abstract
High-k material charge trapping nano-layers in flash memory applications have faster program/erase speeds and better data retention because of larger conduction band offsets and higher dielectric constants. In addition, Ti-doped high-k materials can improve memory device performance, such as leakage current reduction, k-value enhancement, and breakdown voltage increase. In this study, the structural and electrical properties of different annealing temperatures on the Nb2O5 and Ti-doped Nb2O5(TiNb2O7) materials used as charge-trapping nano-layers in metal-oxide-high k-oxide-semiconductor (MOHOS)-type memory were investigated using X-ray diffraction (XRD) and atomic force microscopy (AFM). Analysis of the C-V hysteresis curve shows that the flat-band shift (∆VFB) window of the TiNb2O7 charge-trapping nano-layer in a memory device can reach as high as 6.06 V. The larger memory window of the TiNb2O7 nano-layer is because of a better electrical and structural performance, compared to the Nb2O5 nano-layer.
Highlights
Conventional polysilicon floating gate issues have been explored in recent years because of problems related to the downscaling of memory devices [1–5]
High-k materials were chosen as replacements for conventional polysilicon floating gate memory to form metal-oxide-high k-oxide-semiconductor (MOHOS)-type memories [6,7]
To further enhance the memory performance of the device, addition of Ti atoms into trapping layer has been conducted, and some studies [18–23] reported that Ti-doped high-k materials as charge-trapping layers can improve memory device performance such as leakage current reduction, k-value enhancement, program/erase speeds improvement, and charge loss reduction
Summary
Conventional polysilicon floating gate issues have been explored in recent years because of problems related to the downscaling of memory devices [1–5]. High-k materials were chosen as replacements for conventional polysilicon floating gate memory to form metal-oxide-high k-oxide-semiconductor (MOHOS)-type memories [6,7]. Charge-trapping layers using high-k materials have faster program/erase speeds and better data retention because of larger conduction band offsets and higher dielectric constants [12–16].
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