Navigation Task Partitioning in Distributed-Processing Avionics Systems

Abstract

Recent advancements in electronics technology, such as Very High Speed Integrated Circuits (VHSIC) and Very Large Scale Integration (VLSI), have made the use of embedded microprocessors not only feasible, but the most economical approach to designing modern airborne navigation systems. The integration of GPS and JTIDS with existing navigation systems naturally leads to the use of multiple embedded microprocessors. To effectively use multiple processors, a design procedure must be developed to allocate navigation tasks among processors. Procedures exist for evaluating the performance of computer networks once tasks have been allocated. In particular, simulations can be used to determine loadings and identify bottlenecks. However, these methods cannot be applied until considerable detailed design work has been completed. This paper addresses an approach to allocating navigation tasks early in the design process. The methods discussed are based on applying rate-distortion techniques from communication theory to navigation system design. All navigation activities are broken down into elementary functions. Rate-distortion methods are used to assess the impact on rms position and velocity errors of limiting communication bandwidths among elementary functions. Groups of functions that require high-bandwidth communication are assigned to the same microprocessor, while those that can perform effectively with lower-bandwidth links are separated. This approach also allows the trade-offs in function groupings to be quantified so that decisions regarding the use of VHSIC and VLSI can be based on quantitative assessments of benefits.