Navigating in the density plane – achieving flat wafer surface and uniform metal thickness in CMP processes

Abstract

Chemical Mechanical Polishing (CMP) has long been established as a key process in semiconductor manufacturing. In particular, it is indispensable for the fabrication of copper Dual Damascene metallization structures used almost invariably in modern technologies. Ideally, it results in a planar wafer surface and uniform metal thickness across the chip and wafer in all metal layers. It is however well-known that metal density and possibly other layout properties have some effect on CMP and have to be controlled carefully to achieve satisfactory results. In the first part of this work, we will carefully characterize those dependencies using a series of Virtual Testchips (VTCs). By application of CMP simulation, critical layout properties will be identified, and their effect on CMP results under different process models will be compared. In the second part, we will demonstrate the development of a dummy metal fill algorithms aimed at achieving the best possible results in terms of surface planarity and metal thickness, taking into account the properties of the CMP model as well as constraints from process design rules, native chip layout, and the electrical influence of fill structures.