Narrow Bandwidth PLL Based Multiplier Phase Detector for PSK Modulator

Abstract

Among digital to analog modulation, phase shift keying is superior than amplitude shift keying and frequency shift keying. Especially, the quadrature phase shift keying is the most popular modulating technique. The reason is because this modulation is effective in bandwidth usage. However, the sudden change in amplitude during inversely phase changed, e.g. $\pi/4\Rightarrow-3\pi/4$, requires more bandwidth for transmitting signal. Later, a QPSK modulator based phase locked loop (PLL) [6] is proposed which shows that its QPSK signal consumes less bandwidth compared to the conventional QPSK modulator [7], [8]. However, further study of [6] founds that redundant high frequency components exist in the output of phase detector (PD). In this paper, a new structure of PD of the PLL is proposed which is based on a multiplier circuit. The mathematical analysis of this circuit shows that there is only one high frequency component in the PD output. The simulation result also confirms well with the theoretical analysis which is found that the proposed PD can reduce roughly 29% of bandwidth usage compared to that of [6]. When this PLL based the proposed PD is applied for QPSK modulator, it results in less interference of the QPSK output than that of [6] and [7]. The obtained QPSK signal is superior in reducing the amount of interference to adjacent signals.