Abstract
Message routing networks are acknowledged to be one of the most critical portions of massively parallel computers. This paper presents a processor chip for use in a massively parallel computer. The programmable approach used in this processor provides enough flexibility to make it a “universal” part for building a wide variety of interconnection networks and routing algorithms. A SIMD control scheme is used to make programming and synchronizing large numbers of processors simple. In the course of designing this processor, we were faced with the decision of which logic operations to implement in an Arithmetic-Logic Unit (ALU); informal design studies showed that it was best to provide none. The processor performs all computations by a sophisticated table lookup mechanism, and has no ALU; it is thus called the No ALU Processor (NAP). Using tables rather than an ALU provides a very flexible instruction set, and in real programs often allows more than one “operation” to be done in one cycle. Benchmarks written for the NAP show that indirect addressing mechanisms can speed many common operations by a factor of about log N on an N-processor machine. We have therefore provided hardware to support indirect addressing, or a Multiple Address Multiple Data operation. In addition, the NAP contains local storage used for flexible instruction decoding: the same instruction can result in different operations on different chips. These two mechanisms allow programmers to write programs for NAP machines easily using SIMD style, and also provide the power of different computations happening simultaneously in different parts of the machine. It is possible to build and efficiently simulate, using NAP chips, a wide variety of communications networks, including hypercubes, butterflies, fat-trees, and networks for computing parallel prefix operations. By this informal measure, the NAP architecture is a universal part for building interconnection networks and running network algorithms.
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