Nanostructural Investigation on GaAs//Indium Tin Oxide/Si Junctions for III-V-on-Si Hybrid Multijunction Cells

Abstract

Hard X-ray photoemission spectroscopy (HAXPES) measurements and transmission electron microscopy (TEM) observations are performed on GaAs thin film//Indium tin oxide (ITO)/Si junctions fabricated by surface-activated bonding and selective wet etching. Both of the Ga-O/Ga-As ratio in the Ga 2p3/2 HAPES core spectrum (Fig. 1(a)) and As-O/As-Ga ratio in the As 2p3/2 HAXPES core spectrum (Fig. 1(b)) demonstrate that the GaAs layers are oxidized after annealing at 400 °C. This observation is consistent with the formations of a ~1-nm-thick intermediate layer in the cross-sectional TEM image of the junctions after the 400 °C annealing, as is shown in Figs. 2(a) and 2(b). It is found by using in-house X-ray photoelectron spectroscopy in combination with Ar+ bombardment that the oxide layers are formed at GaAs//ITO bonding interfaces after annealing at 200 °C or higher temperatures. The observation of the oxide layers corresponds with the onset of resistivity increase in GaAs//ITO/Si junctions due to the annealing [1]. These results suggest that annealing brings about the reaction between GaAs and ITO layers and hence the oxidation of GaAs layers, which causes the degradation of the electrical properties of GaAs//ITO/Si junctions. A fabrication process at lower temperatures is likely to be required so as to fully exploit the advantage of ITO as intermediate layers in III-V//Si hybrid tandem solar cells with lower series resistance.[1] Tomoya Hara, Tomoki Ogawa, Jianbo Liang, Kenji Araki, Takefumi Kamioka, and Naoteru Shigekawa, "Electrical properties of GaAs//indium tin oxide/Si junctions for III-V-on-Si hybrid multijunction cells", Jpn. J. Appl. Phys. 57, 08RD05 (2018). DOI: 10.7567/JJAP.57.08RD05 Figure 1