Nanoscale Topography Characterization for Direct Bond Interconnect

Abstract

Hybrid bonding achieves mechanical and electrical connection between device wafers or dies, by directly joining dielectric and metal surfaces to form an all-inorganic interface. This direct bond interconnect (DBI) technology enables very fine pitch interconnects for high bandwidth interfaces. DBI is currently used for mass production of image sensors and is actively investigated for NAND, DRAM and MEMS applications. Characterizing and controlling nanoscale topography are essential for this type of bonding. After chemical mechanical polishing (CMP), the dielectric surface (usually SiO2) should have high planarity and sub-nm roughness, and the metal surface (usually Cu) should be slightly recessed below the dielectric surface in general. Atomic force microscopy (AFM) is a critical technique required to monitor the CMP process module and ensure a robust manufacturing process. While AFM and related techniques have been known for decades, nanoscale or sub-nm scale characterization for DBI requires careful choice of the analysis configurations and parameters to avoid misinterpretation. Here we discuss key considerations for AFM analysis, extraordinary AFM artifacts in the relative heights of the Cu and SiO2 areas, and topographic characteristics of Cu/SiO_2 surface for successful hybrid bonding. The force between an AFM tip and a sample should be sufficiently low for consistent roughness measurement but sufficiently high for minimizing the effects of surface contamination or artifacts. Proper data processing such as flattening should be done to make realistic images. Occasionally we observed artifacts that produced an incorrect Cu height, which could render an actually recessed Cu area as protruding. This artifact tends to occur more if the tip is not fresh or the tapping force is low. If a data image is unusually blurry and the oxide roughness is much smaller than usual, it may be a sign of this artifact. Replacing the tip or scanning in contact mode can usually demonstrate if there was an artifact. AFM analysis revealed that a curved SiO2 surface (oxide rounding) tends to occur in the vicinity of Cu interconnect areas. Optimized CMP conditions can reduce the size of seams and eliminate them.