Nanoscale Strained Si/SiGe Heterojunction Trigate Field Effect Transistors

Abstract

Strained Si surrounding the SiGe embedded body on a silicon on insulator (SOI) substrate forms a novel trigate field effect transistor (FET). The mobility in the channel is enhanced due to the strain of the Si channel. The strained Si trigate FET includes an SOI substrate, an SiGe embedded body, a strained Si channel surrounding layer, an oxide layer, a poly-Si gate electrode (or metal gate electrode), a source, and a drain. This novel device with enhanced carrier mobility and heterojunction confinement is demonstrated to show greatly improved performance for n-type metal–oxide–semiconductor (NMOS) by three dimension simulation. The p-type metal–oxide–semiconductor (PMOS) is not improved as much as NMOS due to the buried channel at the Si/SiGe abrupt heterojunction. Using a grade-back layer among strained Si and a relaxed SiGe body can significantly improve the performance of PMOS.