Abstract
A simple approach is presented for designing complex oxide mesoscopic electronic devices based on the conducting interfaces of room temperature grown LaAlO3/SrTiO3 heterostructures. The technique is based entirely on methods known from conventional semiconductor processing technology, and we demonstrate a lateral resolution of ∼100 nm. We study the low temperature transport properties of nanoscale wires and demonstrate the feasibility of the technique for defining in-plane gates allowing local control of the electrostatic environment in mesoscopic devices.
Highlights
Nanoscale patterning of electronic devices at the amorphous LaAlO3/SrTiO3 oxide interface using an electron sensitive polymer mask
The technique is based entirely on methods known from conventional semiconductor processing technology, and we demonstrate a lateral resolution of $100 nm
The oxide electron systems share the properties of low dimensionality and electrostatic gatability2 with the conventional semiconductor systems but in addition display a wide range of phenomena such as gate-tunable superconductivity, ferroelectricity, magnetism, and spin-orbit coupling caused by strong electron-electron and electron-lattice interactions in regimes not accessible in semiconductors
Summary
Nanoscale patterning of electronic devices at the amorphous LaAlO3/SrTiO3 oxide interface using an electron sensitive polymer mask. A simple approach is presented for designing complex oxide mesoscopic electronic devices based on the conducting interfaces of room temperature grown LaAlO3/SrTiO3 heterostructures.
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