Abstract
This paper demonstrates a low damage inductively coupled plasma SF6/C4F8 dry etch process for the realisation of nanoscale molybdenum gate lines. The optimised process is capable of defining 30nm lines in 100nm thick molybdenum films, with no observable degradation of the mobility of an InGaAs/InAlAs high electron mobility transistor structure which was subjected to the etch. These characteristics make the process reported here suitable for the realisation of short gate length, high performance III–V compound semiconductor transistors.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
