Nanoscale electron beam lithography and etching for fully depleted silicon-on-insulator devices

Abstract

This article describes the process integration and optimization of nanoscale electron beam lithography and etching for the fabrication of fully depleted silicon-on-insulator devices with ultrathin bodies. For the fabrication, standard complementary metal–oxide–semiconductor (CMOS) production line processes with an optimized process flow were supplemented by advanced nanoscale patterning. The nanoscale processes have to fulfill several requirements, such as sub 20 nm exposure with small line edge roughness as well as sub 20 nm highly selective etching with vertical sidewalls. The development and optimization of these fully integrated CMOS processes, which require no additional shrinking step, is shown in this work. 18 nm wide features in calixarene negative tone resist and highly anisotropic etching of sub 30 nm structures with a selectivity to tetraethylorthosilicate of in excess of 300:1 are demonstrated.