Nano-node n-type Gate Dielectric Integrity and Uniformity Correlated to Nitridation Process

Abstract

Mapping technology plus the statistical analysis is a good tool to probe the yield loss of the wafer manufacturing. In this work, the long and short channel devices under the CV measurement with the low and high frequency operation exhibited the interesting performance as the high-k (HK) gate dielectric after the growth of atomic layer deposition (ALD) treated with the post-deposition annealing (PDA) or decoupled plasma nitridation (DPN) process flows. By the way, the electrical performance with drive current, subthreshold swing, gate oxide capacitance and interface state density is also incorporated with the error bar analysis.