Nanometer-Scale Vertical-Sidewall Reactive Ion Etching of InGaAs for 3-D III-V MOSFETs

Abstract

This letter introduces a novel inductively coupled plasma-reactive ion etching (ICP-RIE) technique based on a BCl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiCl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> /Ar chemistry for fabricating sub-20 nm diameter InGaAs nanowires with smooth, vertical sidewall and high aspect ratio (>10). To mitigate dry-etch damage, RIE is followed by a digital etch method comprised of multiple cycles of self-limiting low power O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma oxidation and diluted H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> SO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> rinse. Using these technologies, we demonstrate vertical InGaAs gateall-around nanowire MOSFETs with 30 nm diameter. Digital etch improves both the subthreshold swing and peak transconductance, indicating enhanced sidewall interfacial quality. The combination of RIE and digital etch techniques proposed here is promising for future 3-D III-V MOSFETs.