Abstract

Silicides, widely used as contacts in complementary MOS (CMOS) devices, are expected to introduce large distortions in the underlying silicon, which may have an impact on the device performances. In this work, we employed the convergent beam electron diffraction (CBED) technique in a TEM to map stress in the silicon active areas in structures with different channel lengths spaced by differently sized stripes of two different silicides, NiSi and CoSi 2. In this way, the influence of both composition and size on stress in the silicon was separately analysed and compared to finite element simulations. The results on CoSi 2 indicate presence of tensile stress in the Si region below the gate, gradually turning to compressive as the distance between the silicide layers increases. NiSi layers appear to introduce a lower stress than CoSi 2. Asymmetric stress distribution in NiSi structures appears to be related to the different morphology (possibly grain orientation) of the silicide/Si interfaces. CBED patterns with split diffraction lines, which hinders stress analysis, were recorded at shallow depths below the gate/Si interface.

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