Abstract
We developed a fabrication process for embedding a dense array (108 cm−2) of high-aspect-ratio silicon nanowires (200 nm diameter and 10 μm tall) in a dielectric matrix and then structured/exposed the tips of the nanowires to form self-aligned gate field emitter arrays using chemical mechanical polishing (CMP). Using this structure, we demonstrated a high current density (100 A cm−2), uniform, and long lifetime (>100 h) silicon field emitter array architecture in which the current emitted by each tip is regulated by the silicon nanowire current limiter connected in series with the tip. Using the current voltage characteristics and with the aid of numerical device models, we estimated the tip radius of our field emission arrays to be ≈4.8 nm, as consistent with the tip radius measured using a scanning electron microscope (SEM).
Highlights
Dense arrays of silicon nanowires embedded in a dielectric matrix are exciting structures with a potentially broad range of applications that include electronics and optoelectronic devices
We report on a process for fabricating dense arrays of silicon nanowires that are embedded in a dielectric matrix and integrated with arrays of self-aligned gate field emitters
Characteristics, we see that the arrays do show good agreement with each other when scaled by the number of tips in the array
Summary
Dense arrays of silicon nanowires embedded in a dielectric matrix are exciting structures with a potentially broad range of applications that include electronics and optoelectronic devices. None of the previous work of integrating silicon pillars into field emitter arrays has been able to simultaneously achieve a high current, high current density, and a low voltage while maintaining a long lifetime; this is due to the lack of a fabrication process that could simultaneously build dense, high-aspect-ratio silicon nanowires with sharp emitter tips and integrated, self-aligned extraction gates. The array of field emitters with tip radii less than 5 nm are integrated with dense (1 μm pitch) high-aspect-ratio silicon nanowires (∼200 nm diameter, 10 μm tall) These devices have demonstrated a current >10 mA, a current density >100 A cm−2 and an operating voltage, VGE,OP < 60 V. We report on a new approach for determining the tip radii distribution in field emitter arrays that is based on current voltage characterization
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