Abstract
We report a novel nanocrystal-embedded-insulator (NEI) ferroelectric field-effect transistor (FeFET) with very thin unified-ferroelectric/dielectric (FE/DE) insulating layer, which is promising for low-voltage logic and non-volatile memory (NVM) applications. The ferroelectric nature of the NEI layers comprising orthorhombic ZrO2 nanocrystals embedded in amorphous Al2O3 is proved by polarization voltage measurements, piezoresponse force microscopy, and electrical measurements. The temperature dependent performance and endurance behavior of a NEI negative capacitance FET (NCFET) are investigated. A FeFET with 3.6 nm thick FE/DE achieves a memory window larger than 1 V, paving a pathway for ultimate scaling of FE thickness to enable three-dimensional FeFETs with very small fin pitch.
Highlights
Field-effect transistors with a ferroelectric gate insulator layer (FeFETs) have attracted considerable interest for a variety of integrated circuit applications
The negative capacitance FET (NCFET) exhibit little hysteresis indicating the good matching between the ferroelectric capacitance and the MOS capacitance in the transistors
The NCFETs show the negative capacitance (NC) effect induced clockwise in the current-voltage (I-V) loops, which is in contrast to the counterclockwise ones by charge trapping/detrapping [17]
Summary
Field-effect transistors with a ferroelectric gate insulator layer (FeFETs) have attracted considerable interest for a variety of integrated circuit applications. Due to its inherent negative capacitance (NC) properties, a FeFET can achieve steeper switching behavior than a conventional MOSFET, enabling lower voltage operation [1]. Various channel structures [2–4] and materials [5–7] have obtained sub-60 mV/decade subthreshold swing (SS). Hysteresis in the current-voltage (I-V) characteristic due to remnant polarization (Pr) can be used for non-volatile memory (NVM) application [8]. Material development for FeFETs recently has focused on polycrystalline-doped HfO2 due to its better thickness scalability [9] and CMOS process compatibility [2]. There still exists a fundamental limit for HfO2 thickness scaling to avoid undesired gate leakage current; this in turn limits the FinFET [2]. Inspired by the nanocrystal MOS and memory device concept [10, 11], an insulating
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
