N-Type Nanosheet FETs without Ground Plane Region for Process Simplification.

Khwang-Sun Lee,Jun-Young Park

doi:10.3390/mi13030432

Abstract

This paper proposes a simplified fabrication processing for nanosheet Field-Effect Transistors (FETs) part of beyond-3-nm node technology. Formation of the ground plane (GP) region can be replaced by an epitaxial grown doped ultra-thin (DUT) layer on the starting wafer prior to Six/SiGe1−x stack formation. The proposed process flow can be performed in-situ, and does not require changing chambers or a high temperature annealing process. In short, conventional processes such as ion implantation and subsequent thermal annealing, which have been utilized for the GP region, can be replaced without degrading device performance.

Highlights

TheThe proposed proIn we propose proposeaafabrication fabricationprocess processflow flow proposed cess flow does not treatment, which whichare are process flow does notrequire requireion ionimplantation implantationor or additional additional thermal thermal treatment, conventionallyperformed performedto toform formthe theGP
Layer is doped with a p–type dopant to minimize the parasitic channel layer is doped with a p–type dopant to minimize the parasitic channeland and punch-through floor nanosheet
The fabrication process for nanosheet Field-Effect Transistors (FETs) was newly suggested based on 3-D simulation

Summary

Introduction

N-Type Nanosheet FETs withoutGround Plane Region for ProcessSimplification. Micromachines 2022, 13, 432. https://doi.org/10.3390/ mi13030432Academic Editor: Chengyuan DongReceived: 11 February 2022Accepted: March 2022Published: March 2022Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.Licensee MDPI, Basel, Switzerland. Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations

Methods

Discussion

Conclusion